# Johnson digital counter circuit diagram using D flip flop 7474 (3 bit/4 bit) with animation/ simulation

By
Jaseem Vp

The Johnson digital counter or Twisted Ring Counter is a synchronous shift register with feedback from the inverted output (Q’) of the last flip-flop. Q’ of the last flip flop is connected back to the input D of the first flip-flop. This inversion of Q before it is fed back to input D causes the counter to “count” in a special way. Animation/ simulation of this Johnson counter circuit is also given in this article.You can create simple dancing LED effects using this synchronous Johnson digital counter .The main benefit of this type of counter is that it only needs half the number of flip flops compared to that of standard ring counter to represent many states. So an n-stage Johnson counter givies a sequence of 2n different states and can therefore be treated as a “Mod 2n counter” whereas an n-stage ring counter has only n states that is “Mod n counter”.
Related counter circuits:
Ring Counter Circuit Working Principle with Animation and Video
Binary Up Counter Circuit with working animation and simulation video
Circuit diagram
johnson digital counter circuit
Components required
7474 D flip flop x 2
Resistors (100Ω -1/4 watt x 4)
Astable multivibrator (3 KHz) LEDs x 3
Working of twisted ring counter
Above circuit diagram represents a 3 bit Johnson counter using 7474 D flip flop. You can easily extent this circuit upto 4 bit, 5 bit, etc. by adding flip flops after the 3rd flips flop.
A single 7474 IC consists of 2 flip flops so you need two 7474 ICs for implementing Johnson counter.
Initially all the flip flops are cleared, so the time inverted output (Q’) of 3rd flip flop is high or logic 1.
This logic 1 is appears at the input of 1st flip flop. During the first clock pulse this logic 1 is transferred to the output of 1st flip flop. Thus the total output of Johnson counter is 100.
Then input of 1st and 2nd flip flop is logic 1 and after the second clock pulse these inputs appear at the outputs of 1st and 2nd flip flop. So the total output is 110.
Similarly for the next clock pulse, the output will be 111.
During this state (111) the time inverted output (Q’) is logic 0. This 0 is fed to the 1st flip flop. Then the 0 will circulate through the flip flops as 011,001,000.
In the above circuit either you can connect the Set pin (S pin) to Vcc or you can leave it free.
Feed a 3Hz (or any) 555 astable oscillator to the clock input to start counting.
Johnson counter truth table
Q0
Q1
Q2
0
0
0
State 0
1
0
0
State 1
1
1
0
State 2
1
1
1
State 3
0
1
1
State 4
0
0
1
State 5
After state 5, the circuit goes to state 0 and this will repeat.